1. Field of the Invention
The present invention relates to an information processing system, such as a personal computer (PC), and in particular to an information processing system with a power saving function that reduces the operating frequency of a processor (e.g., central processing unit (CPU)), or that halts the operation of the processor in order to reduce power consumption.
2. Description of Related Art
Various types of personal computers (hereafter referred to as "PCs" or "systems"), such as desktop and notebook computers, are currently being manufactured and sold. The notebook PCs that are being manufactured are compact and light, since portability and outdoor use are taken into consideration for their design.
Power Management of a Personal Computer
One of the features of notebook PCs is that they are battery operated and can be used at sites where there are no commercially available power sources. A battery that is incorporated in a notebook PC is commonly formed as a "battery pack", which is a package that is comprised of a plurality of rechargeable battery cells (also called a "secondary cell"), such as Ni--Cd, NiMH, or Li-Ion. Although such a battery pack is reusable by being charged, its duration for powering a notebook PC is only two to three hours. Therefore, various ideas for power saving have been implemented in order to extend the duration of the incorporated battery pack. The power saving function can be another feature of a notebook PC.
At present, from an ecological point of view, the demand for power saving is increasing, even for desktop PCs to which power can be supplied almost endlessly by commercially available power sources. In June 1993, the U.S. Environmental Protection Agency (EPA) advocated the self-control action that is called the "Energy Star Computer Program", and required that power consumed in the standby state be less than a predetermined value (driving power is to be 30 W or lower, or 30% or less than it is when the CPU is active). Computer makers have developed and manufactured products that conform to the restriction suggestions. For example, desktop PCs that have a power saving function are already sold by IBM (e.g., the PS/55E (for which "Green PC" is a common name), IBM PC 750, and the Aptiva series ("Aptiva" is a trademark of IBM Corp.)).
Power saving with a PC can be accomplished by, for example, reducing power consumption of the individual electric circuits during the operation. Power savings can also be provided by reducing or halting, as needed, the power supply to the individual electric circuits (or devices) in accordance with the reduction of their activity. The latter power saving function may especially be called a "Power Management" function.
The power management modes of a PC are, for example, an "LCD backlight-OFF" mode and an "HDD-OFF" mode, which halts the power supply to devices, such as a liquid crystal display (LCD) and its backlight, or a hard disk drive (HDD), that account for the greatest share of the total power consumption by a full system. Other example power management modes are a "CPU slow clock/stop clock" mode, in which the operating frequency of a CPU is reduced or the operation of the CPU is halted, and a "Suspend" mode. In a Suspend mode, the power supplied to all the electric circuits, except for a main memory, is halted after the necessary data are saved in the main memory.
Power Management Function of a CPU
As is well known, CPUs are the units that constitute the nuclei for the computations that are performed by computer systems. Recently, according to the improvement of techniques for manufacturing semiconductor devices, the operational frequencies of CPUs have increased even further. For example, there have appeared CPU chips that can be driven at operational frequencies that exceed 100 MHz. One example is the "Pentium" processor sold by Intel Corp., and another example is the "PowerPC" processor ("PowerPC" is a trademark of IBM Corp. PowerPC is jointly developed by IBM Corp., Motorola Corp. and Apple Corp.). The performance of a CPU and its operating frequency are very closely related. And as the operational speed of a CPU rises, the calculating speed also increases accordingly. A fast CPU demonstrates its excellent capability especially when running large application programs and when performing graphics procedures.
However, the high processing speed of the CPU brings several problems. One of the problems concerns the increased power consumption by the CPUs and the consequent heat generation. As the intensity of a current that flows across a transistor (i.e., a resistor) per unit time increases, the power consumption and the heat generation also increase. Theoretically, the power that is consumed by a CPU is proportional to the operating frequency. Currently, the ratio of the power consumption of a CPU to the total power consumption by the system cannot be ignored.
The power management functions of the CPU, such as the "CPU slow-clock/stop-clock," are provided to overcome the above described condition. The "slow-clock" and the "stop-clock" are modes in which, when it is determined that the CPU is in the standby state because key input or mouse input has not been performed for more than a predetermined time, power consumption is reduced by lowering the operating frequency of the CPU, or by halting its operation (i.e., the performance of the CPU is lowered). However, it should be noted that the performance of the CPU can be lowered only up to the point at which neither turn-around time (i.e., the time that elapses from the reception of a request until the generation of an affirmative response) nor through-put (the amount of jobs per unit time) is reduced.
The slow clock function of the CPU can be achieved by changing the frequency of a clock signal that is inputted by an external device (for example, an oscillator). This function can also be achieved by changing a CPU chip's internal operating frequency while maintaining a constant externally input clock frequency. A high speed processing CPU ordinarily receives a relatively low clock signal (for example, 66 MHz) and internally increases the speed of an operation clock (to, for example, 133 MHz) by using an incorporated Phase Lock Loop (PLL) circuit. Such a CPU is a so-called "double speed" chip. It is difficult for this type of CPU to drastically change a clock frequency that is inputted by an external device because of the operating property of a PLL circuit (e.g., there is a wait of several milliseconds before a phase lock loop is locked). Therefore, with another method, for a CPU chip that incorporates both a PLL circuit and a slow clock function, the PLL circuit increases an inputted clock speed while the internal slow clock function autonomously lowers the performance of the CPU.
FIG. 1 is a schematic diagram illustrating the arrangement of a CPU that incorporates a power management function. In FIG. 1, a CPU chip 11 comprises a functional unit 11a that performs computation; a PLL circuit 11b that produces, to the functional unit 11a, an operation clock signal for synchronous driving; and a performance controller 11c that controls the performance of the functional unit 11a. The CPU chip 11 communicates with its peripheral devices (not shown) via a processor bus 12.
The function of a PLL circuit whereby the frequency of an input clock signal is multiplied is well known. The PLL circuit 11b accelerates the speed of a relatively slow lock signal (66 MHz, for example) that is inputted from OSC 40 to an operating frequency (133 MHz, for example), and supplies the doubled clock signal to the functional unit 11a.
The functional unit 11a can be divided into a calculation unit 11d and an internal cache/control unit 11e. The calculation unit 11d is a section whose performance can, to a degree, be reduced in accordance with the activity of the system. The internal cache/control unit 11e is a section that must respond to requests, such as a cache snoop, an interrupt request (INTR/NMI/SMI), or a hold request (HOLD), that is issued in a time critical manner and nonperiodically, and, thus, its performance cannot be easily reduced even if the activity of the system is lowering.
The performance controller 11c controls the performance of the functional unit 11a in response to a control signal STPCLK# that is received from an external device. More specifically, while the STPCLK# is active (i.e., low), the controller 11c halts the supply of the operating clock signal to the calculation unit 11d. The CPU chip 11 is designed such that its performance can be reduced partially. As a modification method, the STPCLK# that is to be inputted to the performance controller 11c is intermittently changed to active (i.e., goes low) to reduce the frequency of the operation clock supplied by the PLL circuit 11b. For example, if the STPCLK# is set active (i.e., goes low) for a predetermined cycle and then the frequency of the operation clock is reduced by one of n times, the performance and power consumption of the calculation unit is reduced to about (n-1)/n. The function that intermittently drives the STPCLK# input operation is generally called "Clock Throttling" or "Frequency Emulation". The STPCLK# is one of the control signals on the processor bus 12.
SL enhanced Intel 486, DX2; s, DX4s, and Pentiums, which are chips that have succeeded the "80486" CPU chip from Intel Corp., have the power saving function that is shown in FIG. 1.
The "stop clock" function is the one in which all clock input is prevented and in which the entire functional unit is halted. The complete stopping of the operational clock can be accomplished by a fully static configuration of the CPU in which a storing and saving function is not required. During the "stop clock" mode, the power consumption of the CPU is, at most, several hundreds of mW.
Another problem that arises as the processing speed of a CPU becomes greater is that there is an increase in the differences between the operating speeds of the CPU and external devices (e.g., a main memory and other peripheral devices). When the speed of the CPU is increased, the speed increase is useless unless the peripheral devices are so designed as to match the increased speed of the CPU. However, it is difficult to eliminate the speed gap between them. For example, the operations performed by a hard disk drive include mechanical operations such as a magnetic head seek, so that any increase in its processing speed is limited. As a result, almost all the peripheral devices are operated asynchronously with the CPU. The communication speed between the CPU and the peripheral devices is determined in accordance with the lower speed of the peripheral devices, so that the CPU is always waiting.
Normally, asynchronous communication between devices is facilitated by handshaking (i.e., by acquiring the timing for data transmission and reception). The manner where the CPU executes the handshaking operation differs in accordance with the types of peripheral devices at the reception source, as is shown in the example in FIG. 2.
When the CPU performs asynchronous communication with a floppy disk drive (FDD), the CPU first instructs a floppy disk controller (FDC) to begin the rotation of a motor (motor ON). The motor is activated by setting a motor-ON bit at I/O port 3F2h of the FDC. Then, 500 msecs later, the CPU transmits a command to the FDC, and thereafter the FDC executes a DMA data transfer from the FDD. After the DMA transfer is completed, the FDC transmits an interrupt request (IRQ6) to the CPU. In response to this request, the CPU reads the status register (I/O port 3F4h) of the FDC to ascertain whether the DMA transfer has been completed without any errors. The above mentioned time out value, 500 msecs, is the time that is required for the rotation of the motor to be stabilized, and is determined based on the specifications for the FDD.
When accessing a keyboard, the CPU first reads the status register (I/O port 64) of a keyboard/mouse controller (KMC), and as a flag, sets the least significant bit of the I/O port 64 to "1". The CPU continues polling the first lower bit for a predetermined time period (for example, 2 seconds) to determine whether or not the keyboard has read the flag and has reset it to "0". If the flag is not reset within the predetermined time period, the program of the CPU (BIOS) jumps to an error routine. The above mentioned time out value, 2 seconds, is determined based on the specifications for the keyboard.
To perform asynchronous communication with a hard disk drive, the CPU first transmits a command (data request) to the HDD, and 200 msecs later the CPU begins the data transfer. The data transfer is performed by units of one sector (=512 bytes) each. Each time the transfer for one sector has been completed, the HDD transmits an interrupt request (IRQ14). The CPU, responsive to the interrupt request, reads the status register (I/O port 1F7h) of the HDD and ascertains whether the data transfer has been completed without any errors. The above mentioned time out value, 200 msecs, is the time that the HDD requires for data buffering, and is determined based on the specifications for the HDD.
As is shown in FIG. 2, most of the handshaking operations include a time counting (time out) routine. During the course of the time counting routine, the CPU inevitably waits until a predetermined time has elapsed. In the above described example, the time out value is 500 msecs for the FDD, 2 seconds for the keyboard, and 200 msecs for the HDD. A compatible computer of the IBM PC/AT series performs the time out routine by permitting the CPU (more specifically, a BIOS that controls the operation of the peripheral devices by employing hardware for asynchronous communication) to count DRAM refresh timer signals. The DRAM refresh timer signals, which are generated by a programmable interval timer (PIT), switches its low/high level every 15.2 .mu.sec. Since the timer signals are outputted at the I/O port 061h, the BIOS accesses the I/O port 061h frequently during a handshaking operation.
As previously mentioned, to perform asynchronous communication, the processing speed is determined in accordance with the slower speed of a peripheral device, and the CPU must wait. From the view point of power management, the performance of the CPU should be reduced during asynchronous communication. The CPU, however, must perform the above described time out function because exact execution of the handshaking operation requires it. If this need is disregarded and a "slow clock" or a "stop clock" is performed, the CPU (more specifically, the BIOS) will obtain an erroneous count for the timer signals (e.g., the DRAM refresh timer signals at the I/O port 61) and will not acquire an exact time out value. As a result, security of the system cannot be maintained. In short, the demands of power management and of system security conflict.
With system security being considered more important, almost all the current PCs operate their CPUs at full speed and in normal mode (i.e., with a high operation clock frequency) during asynchronous communication. The systems are designed so that even when the CPU is being operated in a slow clock mode, the CPU is returned to the normal mode for asynchronous communication. Regardless of how much the activity of the CPU is reduced, power saving procedures involving the CPU cannot begin during asynchronous communication. As a result, even if a CPU chip incorporates the power saving function of FIG. 1, for example, the system can employ this function only when the CPU has entirely fallen into a standby state. The CPU entirely falls into the waiting state only on limited occasions, such as when (1) there is no key input for more than a predetermined time period (see, for example, Japanese Examined Patent Publication No. Hei 06-95303); and when (2) a DMA transfer is performed (during a DMA transfer, the CPU relinquishes the right to control the buses) (see Japanese Unexamined Patent Publication No. Hei 06-266462, for example). When the CPU enters the slow clock mode or the stop clock mode during only such short periods of time, the effect of power management is insufficient. It is desirable to extend the periods during which power saving involving the CPU is performed.